A transceiver, for example a radio transceiver, includes a frequency synthesizer. The frequency synthesizer generates multiple frequencies from an oscillator for processing multiple channels. The oscillator works based on a predefined frequency for each channel. Often, the transceiver includes various digital circuits operating at one or more clock frequencies. It might happen that a harmonic of the clock frequencies interferes with the predefined frequency associated with the oscillator at specific channels. The interference is referred to as oscillator pulling. The oscillator pulling worsens oscillator phase noise, and hence impacts processing of the channels and performance of the transceiver. Therefore, there is a need to minimize impact of the oscillator pulling.
In one existing technique, separate supply and ground pins are used for the digital circuits and the oscillator. In another existing technique, de-coupling capacitors are used to minimize effect of pulling. However, such techniques increase area of a chip. In some cases where area is a limitation such techniques cannot be used.
In yet another existing technique, the clock frequencies of the digital circuits that can cause the oscillator pulling are identified during design phase. The digital circuits are then designed to work at a plurality of clock frequencies so that any one clock frequency from the plurality of clock frequencies can be selected, based on the channel being tuned, to minimize interference with the oscillator. However, the technique fails for the clock frequencies that can cause the oscillator pulling but are not identified during the design phase. Further, changing of the clock frequency of the digital circuit from one frequency to another is limited and often may not be possible. For example, if a system-on-chip includes both a frequency modulation (FM) system and a Bluetooth system, and the harmonics of a clock frequency interfering with the FM system originates in the Bluetooth system, a frequency change might not be feasible.